Baya- AI Enabled SoC Intgration Platform, IP-XACT 1685, UPF, Verilog and VHDL Parsers, Translators & Converters, Datamodel and Re-Writers
Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
If you have any question concerning bug fixes, new features and enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.
This utility has been implemented in order to remove concurrent assignments from a verilog netlist without modifying the functionality. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file which can be directly used from the 'lib' directory in the downloaded tar or ZIP file. Example-
source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
removeassignments -in <input vlog files > -top <name-of-module-to-be-flattened> -out <out vhdl file name > [-f <file-containing-list-of-vlog-files>] [+incdir+<include-path1>+<include-path2> [+define+macro1+macro2]
java com.eu.miscedautils.verilogparser.RemoveAssignments -in <input vlog files > -top <name-of-module-to-be-flattened> -out <out vhdl file name > [-f <file-containing-list-of-vlog-files>] [+incdir+<include-path1>+<include-path2> [+define+macro1+macro2]
Go through the examples to get a better understanding of this tool. Send mails to email@example.com if you need any assistance.
Go to the installation directory i.e the directory where this README file resides and run the runme.csh script.
Get details by executing it as 'removeassignments -help'