Baya- AI Enabled SoC Intgration Platform, IP-XACT 1685, UPF, Verilog and VHDL Parsers, Translators & Converters, Datamodel and Re-Writers
Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
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This utility has been developed for those who wants to convert VHDL design into Verilog. This tool supports almost the widely used VHDL constructs except Record and Physical type data. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file.
source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation directory )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation directory )
vhdl2verilog -in simple_and.vhd -top simple_and_top -out simple_and.v
java com.eu.miscedautils.vhdl2verilog.vhdl2verilog -in simple_and.vhd -top simple_and -out output.v
You can provide multple VHDL files even with wildcard like *.vhd through the -filelist switch. Also, you can exclude files with the -excludefilelist switch which also supports wildcards.
Get details by executing it as 'vhdl2verilog -help'
Send your feedback to firstname.lastname@example.org for further improvement of this tool.
1) Record data type
2) Physical data type- this type of construct is not synthesizable
3) NEXT and EXIT statements in sequential LOOP statements
4) Non-synthesizable constructs like allocator etc are not supported
5) Complex aggregate expression may not get translated properly
6) Behavioral constructs like WRITE, READ, TESTBBENCH etc are not yet supported